Volume 5, Issue 1

Implementation Of 32-Bit Floating Point Arithmetic Unit By Using Verilog.

Author

K. V. Umma Maheshwara Rao*, P G Naveen, K. Usha Rani, G. Amani and A. M. Subhan.

Abstract

A B S T R A C T:

Arithmetic circuits form an important class of circuits in digital systems with the remarkable progress in the very large scale integration (VLSI) circuit technology, many complex circuits, unthinkable yesterday have become easily realizable today. Algorithms that seemed impossible to implement now have attractive implementation possibilities for the future. This means that not only the conventional computer arithmetic methods, but also the unconventional ones are worth investigation in new designs. In this thesis an ARITHMETIC UNIT based on IEEE standard for floating point numbers has been implemented on Spartan3E FPGA Board. The arithmetic unit implemented has a 32-bit processing unit which allows various arithmetic operations such as, Addition, Subtraction, Multiplication, Division and Square Root on floating point numbers.Each operation can be selected by a particular operation code. Simulation of FLOATING POINT ALU has been done by XILINX-ISE.

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K. V. Umma Maheshwara Rao*, P G Naveen, K. Usha Rani, G. Amani and A. M. Subhan. | Implementation Of 32-Bit Floating Point Arithmetic Unit By Using Verilog. | DOI :

Journal Frequency: ISSN 2320-1126, Monthly
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Acceptance Notification: Within 6 days
Subject Areas: Engineering, Science & Technology
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