Volume 7, Issue 1

Performance Analysis of Static Carry Skip Adder Using 22nm Strained Silicon CMOS Technology.

Author

D. Anisha Esther Annabai*, E. Hemalatha, C . Divya, J. Ajayan, A. MuthuKumar and T.Ravichandran.

Abstract

Abstract:

A 256-bit adder was designed using 22nm Strained Silicon CMOS technology which is attractive for future VLSI and ULSI application. Carry Skip adders are widely used in cascaded circuit connection and it also improves the delay of the circuit compared to other adders. In this paper, the performance and an analysis on the delay, power, space and speed of strained CMOS technology based static carry skip adder will be presented. The circuits are simulated using 22-nm high performance CMOS with a low supply voltage of 0.8V using HSPICE software tool. The performance of the adder circuit is analyzed by measuring the key parameters of the circuit such as speed, power and also the effect of temperature on circuit performance is also analyzed.

DOI

https://doi.org/10.62226/ijarst20180129

PAGES : 732-735 | 62 VIEWS | 31 DOWNLOADS

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