Volume 4, Issue 6 · IJARST · ISSN 2319-1783 / 2320-1126

Design of a faster 8T SRAM memory cell

Design of a faster 8T SRAM memory cell is an open-access, peer-reviewed research paper by S.K.V.Prasad* and Rambabu, published in Volume 4, Issue 6 of the International Journal of Advanced Research in Science and Technology (IJARST), a UGC-approved journal (Print ISSN 2319-1783, Online ISSN 2320-1126).

Author

S.K.V.Prasad* and Rambabu

Abstract

This paper discusses the design of read/write assist circuits which are used in a SRAM cell’s design to overcome the cell’s variations. It also explains the variability problems in a SRAM bit-cell and many approaches to address them. The basic operations, SNM concept, and write margin of an SRAM are described theoretically as well as measured in simulation. The write assisted circuit, the Negative Bit-line Voltage Bias scheme, is discussed and implemented at transistor level using a six-transistor (6T) SRAM cell. With the write assisted circuit, the implemented memory array successfully performs a write operation, the condition in which the same operation would fail without the write assisted circuit. During the simulation, this write assisted circuit helps to achieve the negative bias voltage of -70mV on the SRAM’s bit- lines. The cost overhead includes chip area, power consumption and chip area.

DOI

https://doi.org/10.62226/ijarst20150651

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How do you cite this paper?

S.K.V.Prasad* and Rambabu — “Design of a faster 8T SRAM memory cell.” International Journal of Advanced Research in Science and Technology (IJARST), Volume 4, Issue 6. DOI: https://doi.org/10.62226/ijarst20150651.

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