Volume 4, Issue 5 · IJARST · ISSN 2319-1783 / 2320-1126

Implementation of a 4T DRAM element for faster digital system applications.

Implementation of a 4T DRAM element for faster digital system applications. is an open-access, peer-reviewed research paper by Vamsi. J* and B. Rambabu, published in Volume 4, Issue 5 of the International Journal of Advanced Research in Science and Technology (IJARST), a UGC-approved journal (Print ISSN 2319-1783, Online ISSN 2320-1126).

Author

Vamsi. J* and B. Rambabu

Abstract

This paper deals with analysis of average power consumption of dram cell designs for the nanometer scale memories. These DRAMs are used in many modern processors’ internal memory. The major contributor of power in dram is the off state leakage current. Improving the power efficiency of a dram cell is critical for the improvement in average power consumption of the overall system. 3T dram cell, 4T dram cells are designed by using TANNER EDA tool and their average power consumption are compared. Average power consumption, write access time, read access time and retention time of 4T, 3T DRAM cell are simulated and compared on 32 nm technology.

DOI

https://doi.org/10.62226/ijarst20150534

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How do you cite this paper?

Vamsi. J* and B. Rambabu — “Implementation of a 4T DRAM element for faster digital system applications..” International Journal of Advanced Research in Science and Technology (IJARST), Volume 4, Issue 5. DOI: https://doi.org/10.62226/ijarst20150534.

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