Volume 4, Issue 1 · IJARST · ISSN 2319-1783 / 2320-1126

High Speed Symmetric Convolutions based FIR Digital Filter Design

High Speed Symmetric Convolutions based FIR Digital Filter Design is an open-access, peer-reviewed research paper by Kalpana* and KHK RaghuVamsi, published in Volume 4, Issue 1 of the International Journal of Advanced Research in Science and Technology (IJARST), a UGC-approved journal (Print ISSN 2319-1783, Online ISSN 2320-1126).

Author

Kalpana* and KHK RaghuVamsi

Abstract

The main challenging areas in VLSI are performance, cost, testing, area, reliability, delay and power. The demand for portable computing devices and communications system are increasing rapidly. These applications require low power dissipation and low area with high speed for VLSI circuits. Hence it is important aspect to optimize power, area and delay .So these constraints optimization became one of the main challenges. In this paper a Parallel FIR Digital Filter Structures for Symmetric Convolutions Based on Fast FIR Algorithm are designed with area, delay and power efficient. To optimize these structures a data flow HDL model is preferred because of consuming less resources when compare with other modeling schemes. This architecture is authorized in Verilog. Behavior simulation is done by using the ISE simulator and synthesis can be done by using the synthesis Xilinx ISE 9.2i.

DOI

https://doi.org/10.62226/ijarst20150197

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How do you cite this paper?

Kalpana* and KHK RaghuVamsi — “High Speed Symmetric Convolutions based FIR Digital Filter Design.” International Journal of Advanced Research in Science and Technology (IJARST), Volume 4, Issue 1. DOI: https://doi.org/10.62226/ijarst20150197.

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