Volume 3, Issue 4

Design Of Low Power SRAM Cell Using Area Efficient Leakage Control Technique

Author

J. Harini Nayana* and U. Jyothsna

Abstract

In deep submicron technologies, leakage power becomes a key for a low power design due to its ever increasing proportion in chip’s total power consumption. Power dissipation is an important consideration in the design of CMOS VLSI circuits. High power consumption leads to reduction in battery life in case of battery powered applications and affects reliability packaging and cooling costs. We propose a technique called LCPMOS for designing CMOS gates which significantly cuts down the leakage current without increasing the dynamic power dissipation. LCPMOS, a technique to tackle the leakage problem in CMOS circuits, uses single additional leakage control transistor, driven by the output from the pull up and pull down networks, which is placed in a path from pull down network to ground which provides the additional resistance thereby reducing the leakage current in the path from supply to ground. The main advantage as compared to other techniques is that LCPMOS technique does not require any additional control and monitoring circuitry, thereby limits the area and also decreases the power dissipation in active state. Along with this, the other advantage with LCPMOS technique is that it reduces the leakage power to an extent of 91.54%, which is more efficient in aspects of area and power dissipation compared to other leakage power reduction techniques.

DOI

https://doi.org/10.62226/ijarst20140443

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