Volume 3, Issue 3 · IJARST · ISSN 2319-1783 / 2320-1126

Design and Simulation of 256 bit 64-point FFT Using RADIX 4 Algorithm

Design and Simulation of 256 bit 64-point FFT Using RADIX 4 Algorithm is an open-access, peer-reviewed research paper by K. Praveen Kumar 1*, M. Srinivasarao2 and K. Venugopal3, published in Volume 3, Issue 3 of the International Journal of Advanced Research in Science and Technology (IJARST), a UGC-approved journal (Print ISSN 2319-1783, Online ISSN 2320-1126).

Author

K. Praveen Kumar 1*, M. Srinivasarao2 and K. Venugopal3

Abstract

A Parallel and pipelined Fast Fourier transform(FFT) processor for use in
the orthogonal frequency division multiplexer .it is important to develop a
high performance FFT processor to meet the requirements of the real time
and low cost in many different systems. Un like being stored in the
traditional ROM, the twiddle factors in our pipelined FFT processor can be
accessed directly. here we simulated and synthesized the 256 bit 64 point
FFT with radix 4 using VHDL coding and simulation and synthesis done by
Modelsim ISE and Xilinx ISE design suite respectively.

DOI

https://doi.org/10.62226/ijarst20140334

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How do you cite this paper?

K. Praveen Kumar 1*, M. Srinivasarao2 and K. Venugopal3 — “Design and Simulation of 256 bit 64-point FFT Using RADIX 4 Algorithm.” International Journal of Advanced Research in Science and Technology (IJARST), Volume 3, Issue 3. DOI: https://doi.org/10.62226/ijarst20140334.

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