Volume 3, Issue 3

Design and Simulation of 256 bit 64-point FFT Using RADIX 4 Algorithm

Author

K. Praveen Kumar 1*, M. Srinivasarao2 and K. Venugopal3

Abstract

A Parallel and pipelined Fast Fourier transform(FFT) processor for use in
the orthogonal frequency division multiplexer .it is important to develop a
high performance FFT processor to meet the requirements of the real time
and low cost in many different systems. Un like being stored in the
traditional ROM, the twiddle factors in our pipelined FFT processor can be
accessed directly. here we simulated and synthesized the 256 bit 64 point
FFT with radix 4 using VHDL coding and simulation and synthesis done by
Modelsim ISE and Xilinx ISE design suite respectively.

DOI

*

PAGES : 163-171 | 43 VIEWS | 89 DOWNLOADS


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K. Praveen Kumar 1*, M. Srinivasarao2 and K. Venugopal3 | Design and Simulation of 256 bit 64-point FFT Using RADIX 4 Algorithm | DOI : *

Journal Frequency: ISSN 2320-1126, Monthly
Paper Submission: Throughout the month
Acceptance Notification: Within 6 days
Subject Areas: Engineering, Science & Technology
Publishing Model: Open Access
Publication Fee: USD 60  USD 50
Publication Impact Factor: 6.76
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