Volume 2, Issue 3 · IJARST · ISSN 2319-1783 / 2320-1126

Implementation of Area Efficient Barrel Shifter

Implementation of Area Efficient Barrel Shifter is an open-access, peer-reviewed research paper by A.V.S Naidu* and B. Vijayabhaskar, published in Volume 2, Issue 3 of the International Journal of Advanced Research in Science and Technology (IJARST), a UGC-approved journal (Print ISSN 2319-1783, Online ISSN 2320-1126).

Author

A.V.S Naidu* and B. Vijayabhaskar

Abstract

Abstract:

Barrel shifters are often utilized by embedded digital signal processors and general purpose processors to manipulate data. Barrel shifters are widely used where more than one bit shift operation is required in arithmetic and logical operations. The design of barrel shifter is a most challenging task towards its speed, area and power consumption. Here we are going to implement an 8-bit barrel shifter in the form of two approaches and we are going to analyze the circuits in terms of speed area and power consumption. Here the circuits are implemented and analyzed by using the most popular semi-custom design tool VHDL and will be synthesized by using SPARTAN-3 FPGA.

DOI

https://doi.org/10.62226/ijarst20130383

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How do you cite this paper?

A.V.S Naidu* and B. Vijayabhaskar — “Implementation of Area Efficient Barrel Shifter.” International Journal of Advanced Research in Science and Technology (IJARST), Volume 2, Issue 3. DOI: https://doi.org/10.62226/ijarst20130383.

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